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60811 sy/60910 sy/42810 sy 20 1003265-s00003 no.a1699-1/18 http://onsemi.com semiconductor components industries, llc, 2013 june, 2013 LV24250LS overview the LV24250LS is an i 2 c-controlled single-chip fm tuner ic that inte grates external components which are necessary for tuning in a compact vqlp package with dimensions of only 3.5mm3.5mm. features ? fm fe ? fm if ? mpx stereo decoder ? fll tuning ? standby specifications absolute maximum ratings at ta = 25 ? c parameter symbol conditions ratings unit maximum supply voltage v cc max analog block supply voltage 5.0 v v dd max digital block supply voltage 4.0 v maximum input voltage v in 1 max scl, sda, int v dd +0.3 v v in 2 max external_clk_in v dd +0.3 v allowable power dissipation pd max ta ? 70 ? c * 140 mw operating temperature topr -20 to +70 ? c storage temperature tstg -40 to +125 ? c * : when mounted on the specified printed circuit board (40. 0mm 50.0 mm 0.8mm), four layers glass epoxy (2s2p) bi-cmos lsi 1-chip fm tuner ic for compact portable equipment ordering number : ena1699b stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
LV24250LS no.a1699-2/18 operating conditions at ta = 25 ? c parameter symbol conditions ratings unit recommended supply voltage v cc analog block supply voltage 3.0 v v dd digital block supply voltage 3.0 v operating supply voltage range v cc op 2.6 to 3.6 v v dd op 2.5 to 3.6 v v io op interface voltage 2.2 to 3.6 v note : supply voltage v io equal v dd , or v io v dd & v io 2.2 v * stabilize the service voltage so as not to cause the voltage change by the noise etc. operating characteristics at ta = 25c, v cc = 3.0v, v dd = 3.0v, volume =15/16, soft mute = 1/soft stereo = off with the designated test circuit output level set with radio control 1 of control re gister map (0dh bit0, bit1,bit5 set to ?1?, ?1?) control 2 of control register map (0dh bit1 set to ?1?) in addition, set if_osc = 170khz, if_bw = 100% (r adio control 1 : 0d bit6, bit7 set to ?1?, ?1?) parameter symbol conditions ratings unit min typ max current drain (in operation) i cc a analog block at 60db ? v emf input 12 17 ma i cc d digital block at 60 db ? v emf input 0.3 0.8 ma current drain (in standby) i cc a analog standby mode 3 30 ? a i cc d digital standby mode 3 30 ? a fm receive band f_range refer to pcb mounting conditions to cover the fm receive band of 76m to 108mhz 76 108 mhz fm receive characteristics; mono : fc = 80mhz, fm = 1khz, 22.5khzdev. note that soft_m ute = 1, soft_stereo function off, ihf-bpf used 3db sensitivity -3db ls 60db ? v, 22.5khzdev output standard, -3db input. 5 17 db ? v emf practical sensitivity 1 qs1 input at s/n = 30db de-emphasis = 75 ? s, sg open display 8 16 db ? v emf practical sensitivity 2 (reference) qs2 input at s/n = 26db de-emphasis = 75 ? s, sg terminal display 1.10 ? v demodulation output vo 60db ? v emf, pin 19 output 80 110 160 mvrms channel balance cb 60db ? v emf, pin 18 output/pin 19 output -2 0 2 db signal-to-noise ratio s/n 60db ? v emf, pin 19 output 48 58 db total harmonic distortion 1 (mono) thd1 60db ? v emf, pin 19 output, 22.5khz dev. 0.4 1.5 % total harmonic distortion 2 (mono) thd2 60db ? v emf, pin 19 output, 75.0khz dev. 1.3 3 % field intensity display level fs reg1dh_bit0 = off input level at which reg02h_bit1-3 change from 1 to 2. 3 10 20 db ? v emf mute attenuation mute-att. 60db ? v emf, pin 19 output 60 70 db fm receive characteristics ; stereo characteristics : fc = 80mhz, fm = 1khz, v in = 60db ? v emf, pilot = 10% (7.5khzdev), mpx-filter used separation sep l-mod, pin 19 / pin 18 output l+r signals = 30% (22.5khz dev.) 20 35 db total harmonic distortion (main) thd-st1 main-mod (for l + r input), 19 output ihf_bpf l+r signals = 30% (22.5khzdev.) 0.6 1.8 % interface block allowable operation range at ta = -20 to +70 ? c, v ss = 0v parameter symbol conditions ratings unit min typ max supply voltage v dd 2.5 3.6 v digital block input v ih high-level input voltage range 0.7v dd v dd v v il low-level input voltage range 0 0.1v dd v digital block output i ol output current at low level 2.0 ma v ol output voltage at low level i ol = 2ma 0.6 v external clock operating frequency fclk_ext cloc k frequency for external input 32k 32.768k 20m hz note : external clock input (pin 12) allo ws also input of the sine wave signal.
LV24250LS no.a1699-3/18 package dimensions unit : mm (typ) 3393 pin assignment sanyo : vqlp24j(3.5x3.5) 3.5 0.35 0.2 0.4 3.5 0.35 (0.1) (0.054) (0.75) (0.75) 0.85 max 0.0 nom side view top view side view bottom view 1 2 24 line_out_l package-gnd package-gnd package-gnd package-gnd gnd 1 ext_clk_in package-gnd package-gnd package-gnd top view package-gnd scl fm_ant1 fm_ant2 vio v dd int sda line_out_r mpx_out nc fll_lpf vstabi v cc 2 3 16 4 5 6 18 17 15 14 13 12 11 10 9 8 7 19 20 21 22 23 24
LV24250LS no.a1699-4/18 block diagram line_out_l package_gnd package_gnd package_gnd package_gnd gnd ext_clk_in buffer amp fm demodulator package_gnd package_gnd package_gnd package_gnd scl fm_ant1 fm_ant2 v io v dd int sda line_out_r mpx_out fll_lpf vstabi nc v cc voltage stabilizer stereo decorder de- emphasis tuning system digital interface i 2 c conversion quadrature oscillator fm selectivity filter rf and fm quadrature mixer to each block to each block tuning fll to each block line sw and mute power manage ment 1 2 3 16 4 5 6 18 17 15 14 13 12 11 10 9 8 7 19 20 21 22 23 24
LV24250LS no.a1699-5/18 pin function pin no. pin name description pin voltage internal equivalent circuit 1 2 fm-ant1 fm-ant2 antenna input for pin 1 single input, pin 2 is set to ac_gnd via capacity 1v 3 v i/o digital interface supply voltage power pin dedicated to the interface input/output elements v i/o 4 v dd digital supply voltage power pin for digital block v dd 5 int interrupt line output pin dedicated to interrupt (hardware output: used for options) 6 sda digital interface data ine bidirectional data line. pull up to vio line with 3.3k ? to 10k ? resistor 7 scl digital interface clock line 8 9 10 11 package-gnd gnd for package-shield bnd pin for package shield (gnd) 12 ext_clk_in reference clock-source input for measurement external standard clk input pin. 12 v dd clk v io continued on next page. 3 v_i/o v dd to each interface block 4 v dd to each logic block 1 2 1v 1v 1v 1v mixer mixer ant1 ant2 vstabi vstabi 5 int v dd v io 6 v dd data data v io 7 v dd scl v io
LV24250LS no.a1699-6/18 continued from preceding page. pin no. pin name description pin voltage supplement 13 v cc analog supply voltage power pin for analog (tuner) block v cc 14 vstabi stabilizer voltage local oscillator reference bias pin. nc pin to be used 2.6v . 15 . nc keep this open 16 fll_lpf lpf for fll lpf pin for noise decrease when fll operates. capacity(0.47 f to 1.0 f) is added this pin and between vstabi pin of 14pin. nc pin to be used 17 mpx_out mpx-signal output stereo decoder input monitor pin. nc pin to be used 2.3v 18 line-out-r radio rch line-output audio r_ch output 1.2v 19 line-out-l radio lch line-output audio l_ch output 1.2v 20 21 22 23 package-gnd gnd for package-shield gnd pin for package shield (gnd) 24 gnd gnd (analog and digital gnd) gnd pin for analog (fm tuner) block and digital (control) block (gnd) 13 v cc to each v cc block 26v bias regulater 14 v cc vstabi. line for each block 2.6v bias regulater osc block 13 v cc 16 vstabi 17 vstabi 18 vstabi vstabi 19
LV24250LS no.a1699-7/18 format of bus transfers bus transfers are prim arily based on the i 2 c primitives ? start condition ? repeated start condition ? stop condition ? byte write ? byte read start, restart, and stop conditions are specified as shown in table 1 below. start repeated start stop fig. 1 the i 2 c start, repeated start and stop conditions. for details, like timing, etc., refer to specifications of i 2 c. 8-bit write 8-bit data is sent from the master microcomputer to LV24250LS. data bit consists of msb first and lsb last. data transmission is latched at the rising edge of scl in synchronization with the scl clock generated at the master ic. do not change data while scl remains high. LV24250LS outputs the ack bit between eighth and ninth falling edges of scl fig. 2 signal pattern of the i 2 c byte write read is of the same form as write, only except that the data direction is opposite. eight data bits are sent from LV24250LS to the master while ack is sent from the master to LV24250LS. fig. 3 signal pattern of the i 2 c byte read the serial clock scl is supplied from the master side. it is essential that data bit is output from LV24250LS in synchronization with the falling edge while the mast er side performs latching at the rising edge. scl sda scl sda scl sda scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack scl sda d7 d6 d5 d4 d3 d2 d1 d0 ack
LV24250LS no.a1699-8/18 LV24250LS latches ack at the rising edge. the sequence to write data d into the re gister a of LV24250LS is shown below. ? start condition ? write the device address (c0h) ? write the register address, a ? write the target data, d ? stop condition fig. 4 register write through i 2 c when one or more data has been provided for writing, only the first data is allowed to be written. read sequence ? start condition ? write the device address (c0h) ? write the register address, a ? repeated start condition (or stop + start in a single master network) ? write the device address + 1 (c1h) ? read the register contents d, tran smit nack (no more data to be read) ? stop condition fig. 5 register read through i 2 c interrupt pin int LV24250LS has the dedicated interrupt output pin. for the active level to the host, either low or high can be selected. the int output pin is kept floating while the pwrad bit is cleared during initialization. therefore, to avoid influence on the cpu side during initia lization, it is recommended to secure the non-active state by means of the pull-up or pull-down resistor. this enables direct int output connection to non-masking interruption of the host cpu. scl sda da7 start write device address write register address stop write data byte da6...1 ack a7 a6...1 d7 d6...0 ack ack scl sda da7 start write device address rep. write register address write device address + 1 stop start read data byte with nack da6...1 ack a7 a6...0 da7 da6...1 d7 d6...0 ack ack
LV24250LS no.a1699-9/18 digital interface specification (interface specification : reference) (1). characteristics of sda and scl bus line relative to the i 2 c bus interface parameter symbol standard-mode high_speed-mode unit min max min max scl clock frequency f scl 0 100 0 400 khz fall time of both sda and scl tf 300 20+0.1cb 300 ns rise time of both sda and scl tr 1000 20+0.1cb 300 ns high time of scl t high 4.0 0.6 ? s low time of scl t low 4.7 1.3 ? s hold time of stat condition t hd ; st a 4.0 0.6 ? s hold time of data t hd ; dat 03.45 0 0.9 ? s set-up time of stat condition t su ; st a 4.7 0.6 ? s set-up time of stop condition t su ; sto 4.0 0.6 ? s set-up time of data t su ; dat 250 100 ns bus free time between a stop and t buf 4.7 1.3 ? s capacitivie load for each bus line cb 400 400 pf *cb = total capacitance of one bus line (2). register map (on register map) following is sub address map of LV24250LS. each register becomes 8-bit constitution. address register name mode remark 00h chip_id r/w chip id 02h radio_stat r status of radio station 0bh rfcap r/w rf cap bank 0dh radio_ctrl1 r/w radio control 1 0eh radio_ctrl2 r/w radio control 2 0fh radio_ctrl3 r/w radio control 3 10h tnpl r tune position low 11h tnph_stat r tune position high and status 19h ref_clk_prs r/w reference clock pre-scalar 1ah ref_clk_div r/w reference clock divider 1bh ref_clk_off r/w re ference clock offset 1dh scn_ctrl r/w scan control 1eh target_val_l r/w target value low 1fh target_val_h r/w target value high r : read only register r/w : read and write register scl sda t high repeated star t t su;sta t hd;dat t su;dat t hd;sta t low tr start condition tf tf tr
LV24250LS no.a1699-10/18 (3). register description (on contents of each register) register 00h ? chip_id ? chip id entify register (read/write) 7 6 5 4 3 2 1 0 id [7 : 0] bit 7-0 : id [7 : 0] : 8-bit chip id. LV24250LS : 15h note : to abort the command, write any value in this register. register 02h ? radio_stat ? radio station status (read-only) 7 6 5 4 3 2 1 0 rad_if n/a n/a mo_st fs [2 : 0] sf5db bit 7 : rad_if : radio interrupt flag. 0 = no interrupt 1 = interrupt note : when status (field strength, ster eo/mono) changes, this bit is set. if interrupt of irq pin is enabled, interrupt pi n is set by following ipol register condition. this bit is cleared by register read. in stand-by mode (pw_rad = 0), this bit is 1 bit 6-5 : na [1 : 0] : na 0 fixed bit 4 : mo_st : mono/stereo indicator 0 = forced monaural 1 = normal (receiving in stereo mode) bit 3-1 fs [2 : 0] : fieldstrength : 0 = low field strength ? 7 = high field strength bit 0 : sf5db : fieldstrength +5db : 0 = fs5db no up 1 = fs5db up for details, refer to application note. register 0bh ? rfcap ? rf cap bank (read/write) 7 6 5 4 3 2 1 0 rfcap [7 : 0] bit 7-0 : rfcap [7 : 0] : rf oscillator cap bank
LV24250LS no.a1699-11/18 register 0dh ? radio_ctrl1 ? radio control 1 (read/write) 7 6 5 4 3 2 1 0 if_sel ifbwsel agc_spd deem st_m nmute vol [1 : 0] bit 7 : if_sel : if frequency setting 0 = 150khz 1 = 170khz bit 6 : ifbwsel : if band width setting 0 = 50% 1 = 100% bit 5 : vol_2 : volume setting for details, refer to bit0,1 for radio_ctrl1 bit 4 : deem : de-emphasis 0 = 50 ? s : korea, china, europe, japan 1 = 75 ? s : usa bit 3 : st_m : stereo/mono setting 0 = stereo enabled 1 = stereo disabled (mono mode) bit 2 : nmute : audio mute 0 = mute on 1 = mute off bit 1-0 : vol [1 : 0] : volume setting * it controls by bit5 of radio_ctrl1 and co mbination 4bit with bit1 of radio_ctrl2 . vol_3 vol_2 vol_1 vol_0 0 0 0 0 : minimum level 0 0 0 1 0 0 1 0 ? 1 1 1 1 : max level register 0eh ? radio_ctrl2 ? radio control 2 (read/write) 7 6 5 4 3 2 1 0 softst [2 : 0] softmu [2 : 0] n/a stabi_bp bit 7-5 : softst [2 : 0] : soft stereo setting 000b = soft stereo level 3 001b = disable soft stereo 010b = soft stereo level 1 (*) 100b = soft stereo level 2 note : do not use without these value. (*) : recommended setting bit 4-2 : softmu [2 : 0] : soft audio mute setting 000b = soft audio mute level 3 001b = disable soft audio mute 010b = soft audio mute level 1 100b = soft audio mute level 2 (*) note : do not use without these value. (*) : recommended setting bit 1 : vol_3 : volume setting for details, refer to bit0,1 for radio_ctrl1 bit 0 : stabi_bp : internal regulator by-pass bit 0 = internal regulator operate (normal) 1 = internal regulator by-pass
LV24250LS no.a1699-12/18 register 0fh ? radio_ctrl3 ? radio control 3 (read/write) 7 6 5 4 3 2 1 0 ipol sm_ie rad_ie sd_pm nif_pm ext_clk_cfg [1 : 0] pw_rad bit 7 : ipol : interrupt (irq) polarity 0 = irq active high 1 = irq active low bit 6 : sm_ie : command end interrupt 0 = disable 1 = enable bit 5 : rad_ie : radio interrupt (field strength/stereo changes) 0 = disable 1 = enable bit 4 : sd_pm : stereo decoder clock pll mute 0 = sd pll on (normal operation) 1 = sd pll off (adjustment) bit 3 : nif_pm : if pll mute 0 = if pll off (adjustment) 1 = if pll on (normal operation) bit 2-1 : ext_clk_cfg [1 : 0] : external clock setting ext_clk_cfg [1 : 0] reference clock 00 off 01 na:do not use 10 oscillator clock source / 32 (for high frequency source) 11 oscillator clock source (for low frequency source) bit 0 : pw_rad : radio circuit power 0 = power off (stand-by). 1 = power on note : at the time of start, pw_rad becomes 0 (stand-by) register 10h ? tnpl ? tune position low (read-only) 7 6 5 4 3 2 1 0 tunepos [7 : 0] bit 7-0 : tunepos [7 : 0] : current rf frequency (low 8bit)
LV24250LS no.a1699-13/18 register 11h ? tnph_stat ? tune position high/status (read-only) 7 6 5 4 3 2 1 0 error [2 : 0] sm_if tuned na tunepos [9 : 8] bit 7-5 : error [2 : 0] : error code error [2 : 0] remark 0 ok, command end (no error) 1 default value after or during reset 2 band limit error 3 dac limit error 6 command forced end 7 command busy bit 4 : sm_if : command end interrupt flag 0 = no interrupt 1 = interrupt this bit is set when the command is over. when the irq pin interru pt is allowed, the pin status is changed, reading this regist er causes clearing. bit 3 : tuned : radio tuning flag 0 = no tune 1 = tuned note : this flag is set when tuned or a station search succeeded. this flag is cleared under 3 conditions as below. (1) pw_rad = 0 (2) tuning frequency (3) fm station searching bit 2 : na : 0 (fix) bit 1 : 0 : tunepos [9 : 8] : current rf frequency (high 2 bit) register 19h ? ref_clk_prs ? refer ence clock prescaler (read/write) 7 6 5 4 3 2 1 0 refpre [2 : 0] refmod [4 : 0] bit [7 : 5] : refpre [2 : 0] : reference clock pre- scaler 0 = 1 : 1 1 = 1 : 2 ? 7 = 1:128 bit [4 : 0] : refmod [4 : 0] : 5-bit slope correction register 1ah ? ref_clk_div ? refe rence clock divider (read/write) 7 6 5 4 3 2 1 0 refdiv [7 : 0] bit 7-0 : refdiv [7 : 0] : reference clock divider 0 : divider value = 1 1 : divider value = 2 ? 255 : divider value = 256 register 1bh ?ref_clk_off ? refe rence clock offset (read/write) 7 6 5 4 3 2 1 0 refoffs [7 : 0] bit 7-0 : refoffs [7 : 0] : offset register for the spread of reference clock
LV24250LS no.a1699-14/18 register 1dh ? scn_ctrl ? scan control (read/write) 7 6 5 4 3 2 1 0 grid [1 : 0] fll_on fll_m ode fs [2 : 0] shf5db bit 7-6 : grid [1 : 0] : fm station search frequency interval : 0 = ifsd set 1 = 50khz grid 2 = 100khz grid 3 = 200khz grid bit 5 : fll_on : fll control 0 = fll off 1 = fll on during setting of the fm frequency and during seek, keep this off. turn it on after tuning. bit 4 : reserved : 0 (fix) however, '1' is set when capacity is added to 16pin, and it uses it as smoothing filter(fll_lpf). bit 3-1 : fs [2 : 0] : field strength setting at the time of fm station search and a frequency adjustment bit set 1 for setting of ifsd. bit 0 : shf5db : scan stop level +5db register1eh ? target_val_l ? target value low register (read/write) 7 6 5 4 3 2 1 0 target [7 : 0] bit 7-0 : target [7 : 0] : target frequency low 8 bit : tuning frequency or limit frequency for fm station search register 1fh ? target_val_h ? target value high register (read/write) 7 6 5 4 3 2 1 0 target [15 : 8] bit 7-0 : target [15 : 8] : target frequency high 8 bit : target value of oscillator calibration, tuning frequenc y value or limit frequency value for station search note : grid [1 : 0] is not 0 target [15 : 14] has different definition with radio power on, lower eight bits of the target frequency are set. then, set higher eight bits of the target frequency to t his register. the command is executed.
LV24250LS no.a1699-15/18 test circuit line_out_l top view 1000pf 1000pf package gnd sw sw sw v dd voltage source v io voltage source i 2 c_bus mpu gnd external_clk_in package gnd scl fm_ant v io v dd int sda int extenal clk_in sda (data) scl (clock) line_out_r v cc v cc voltage source + 1 2 3 16 4 5 6 18 17 15 14 13 12 11 10 9 8 7 19 20 21 22 23 24
LV24250LS no.a1699-16/18 application circuit cautions for mounting of ic note1 : for external part constant, the recommended value is described. since the constant may differ during actual use with the set mounted, be sure to consider optimization. note2 : the single input antenna application has been described. the difference input is also possible (the signal input from 1pin and 2pin: refer to the application note for details). note3 : if the spike noise between mpu and ic is large during communication, it is recommended to add limiting resistors r1, r2, and r3 between mpu and ic. 0 ? at 1.8v. note4 : to reduce noise from power supply, add a capacitor between v cc - gnd and between v dd - gnd. note5 : the i 2 c bus communication line requires pull-up resistors r5 and r6. the commonly-employed resistance value is 4.7k (4.7k to 10k). set the pull-up voltage to the same one of v io of LV24250LS. (supply from the same source as v io and v dd is recommended. note6 : please use the int pin arbitrarily. recommended to open when unused. the int pin becomes unstable at ic startup. to protect mpu from any effects during startup, it is recommended to add either the pull-up or pull-down resistor to set the non-active mode. (this is not necessary when the mpu can be set to non-active by a software during initialization. line_out_l top view 100 to 1000pf 47pf package gnd sw sw v dd voltage source i 2 c_bus mpu gnd external_clk_in package gnd scl r6 r5 r1 r2 r3 r4 fm_ant vio v dd int sda int extenal clk_in sda (data) scl (clock) line_out_r v cc v cc voltage source + 27pf 1 2 3 16 4 5 6 18 17 15 14 13 12 11 10 9 8 7 19 20 21 22 23 24 not necessary when the cd cut capacity is on the receive side changeover of resistor possible depending on the state of power supply changeover of resistor possible depending on the state of power supply voltage for i 2 c interface pull-up 120nh winding type
LV24250LS no.a1699-17/18 pcb mounting conditions to cover the fm receiving area of 76m to 108mhz LV24250LS's pcb mounting conditions ? LV24250LS has an inductor for local oscillator on the package bottom side. in order to cover the receiving frequency range of 76mhz to 108mhz, provide the gnd layer to the first layer of side a of pcb that is directly below the package bottom side, as shown in the figure. recommended layout of pcb substrate ic backside_LV24250LS ic directly-below_pcb recommended gnd patten diagram ? with this spl, the receiving frequency is measured under the following conditions : ? the x-value can be set freely between min = 2.00 mm and max = 2.60mm with reference to ic. (the x-value for our demo board is 2.4mm.) ? the y-value can be set freely between min = 1.00 mm and max = 2.40mm with reference to ic. (the y-value for our demo board is 2.30mm.) ? avoid providing another wiring within 0.4mm of bottom layer of pcb_gnd as much as possible. LV24250LS printed circuit board layer x = 0mm 3.50 3.50 0.75 0.20 2.24 0.40 2.64 0.79 3.50 3.50 y = 2.30 0.60 0.60 x = 2.40 0.55 0.55 pcb gnd layer 0.57
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